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STV6886
LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
FEATURES General s SYNC PROCESSOR (separate or composite) s 12V SUPPLY VOLTAGE s 8V REFERENCE VOLTAGE s HOR. LOCK/UNLOCK OUTPUT s HOR. & VERT. LOCK/UNLOCK INDICATION 2 s READ/WRITE I C INTERFACE s HORIZONTAL AND VERTICAL MOIRE s B+ REGULATOR - Internal PWM generator for B+ current mode step-up converter - Switchable to step-down converter - I2C-adjustable B+ reference voltage - Output pulses synchronized on horizontal frequency - Internal maximum current limitation. Horizontal s Self-adaptative s Dual PLL concept s 80kHz maximum frequency s X-ray protection input 2 s I C controls: Horizontal duty-cycle, H-position, horizontal size amplitude Vertical s Vertical ramp generator s 50 to 120 Hz agc loop s Geometry tracking with VPOS & VAMP 2 s I C controls:VAMP, VPOS, S-CORR, C-CORR s Vertical breathing compensation I2C Geometry Corrections s Vertical parabola generator (Pin Cushion - E/W, Keystone, Corner Correction) s Horizontal dynamic phase (Side Pin Balance & Parallelogram) s Horizontal and vertical dynamic focus (Horizontal Focus Amplitude, Horizontal Focus Symmetry, Vertical Focus Amplitude) DESCRIPTION The STV6886 is a monolithic integrated circuit assembled in a 32-pin shrink dual-in-line plastic package. This IC controls all the functions related to horizontal and vertical deflection in multimode or multi-frequency computer display monitors. The internal sync processor, combined with the powerful geometry correction block, makes the STV6886 suitable for very high performance monitors, using few external components. Combined with other ST components dedicated for CRT monitors (microcontroller, video preamplifier, video amplifier, OSD controller) the STV6886 allows fully I2C bus-controlled computer display monitors to be built with a reduced number of external components.
SHRINK32 (Plastic Package) ORDER CODE: STV6886 PIN CONNECTIONS
H/HVIN VSYNCIN HMOIRE/HLOCK PLL2C C0 R0 PLL1F HPOSITION HFOCUSCAP FOCUS-OUT HGND HFLY HREF COMP REGIN ISENSE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
5V SDA SCL VCC BOUT GND HOUT XRAY EWOUT VOUT VCAP VREF VAGCCAP VGND VBREATH B + GND
Version 4.2
April 2000 1/43
1
TABLE OF CONTENTS
PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 QUICK REFERENCE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Supply and reference voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 I2C READ/WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SYNC PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 HORIZONTAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VERTICAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DYNAMIC FOCUS SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 GEOMETRY CONTROL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MOIRE CANCELLATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 B+ SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TYPICAL OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I2C BUS ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 OPERATING DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1 GENERAL CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.2 I2C Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.3 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5 Sync Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6 Sync Identification Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.7 IC status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.8 Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.9 Sync Processor Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2 HORIZONTAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.1 Internal Input Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2 PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4 Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.5 X-RAY Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.6 Horizontal and Vertical Dynamic Focus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.7 Horizontal Moire Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3 VERTICAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2 I2C Control Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3 Vertical Moire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4 Basic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5 Geometric Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.6 E/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.7 Dynamic Horizontal Phase Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4 DC/DC CONVERTER PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1 Step-up Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2 Step-down Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3 Step-up and Step-down Configuration Comparison . . . . . . . . . . . . . . . . . . . . 2 . . . 32 . INTERNAL SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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STV6886
PIN CONNECTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name H/HVIN VSYNCIN HMOIRE/ HLOCK PLL2C C0 R0 PLL1F HPOSITIO N HFOCUSCAP FOCUS OUT HGND HFLY HREF COMP REGIN ISENSE B+GND VBREATH VGND VAGCCAP VREF VCAP VOUT EWOUT XRAY HOUT GND BOUT VCC SCL SDA 5V Function TTL-compatible Horizontal sync Input (separate or composite) TTL-compatible Vertical sync Input (for separated H&V) Horizontal Moire Output (to be connected to PLL2C through a resistor divider), HLock Output Second PLL Loop Filter Horizontal Oscillator Capacitor Horizontal Oscillator Resistor First PLL Loop Filter Horizontal Position Filter (capacitor to be connected to HGND) Horizontal Dynamic Focus Oscillator Capacitor Mixed Horizontal and Vertical Dynamic Focus Output Horizontal Section Ground Horizontal Flyback Input (positive polarity) Horizontal Section Reference Voltage (to be filtered) B+ Error Amplifier Output for frequency compensation and gain setting Feedback Input of B+ control loop Sensing of external B+ switching transistor current, or switch for step-down converter Ground (related to B+ reference) V Breathing Input Control (compensation of vertical amplitude against EHV variation) Vertical Section Ground Memory Capacitor for Automatic Gain Control in Vertical Ramp Generator Vertical Section Reference Voltage (to be filtered to pin 19) Vertical Sawtooth Generator Capacitor Vertical Ramp Output (with frequency-independent amplitude and S or C Corrections if any). It includes vertical position and vertical moire voltages. Pin Cushion (E/W) Correction Parabola Output X-RAY protection input (with internal latch) Horizontal Drive Output (NPN open collector) General Ground B+ PWM Regulator Output (NPN open collector) Supply Voltage(12V typ) (referenced to Pin 27) I2C Clock Input I2C Data Input 5V Supply Voltage
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STV6886
QUICK REFERENCE DATA
Parameter Any polarity on H Sync & V Sync inputs TTL or composite Syncs Sync on Green Horizontal Frequency Horizontal Autosync Range (for given R0 and C0. Can be easily increased by application) Control of free-running frequency Frequency Generator for Burn-in Control of H-Position through I C Control for H-Duty Cycle through I2C PLL1 Inhibition Possibility Output for Horizontal Lock/Unlock Dual Polarity H-Drive Outputs Vertical Frequency Vertical Autosync Range (for 150nF on Pin 22 and 470nF on Pin 20) Vertical S-Correction (adapted to normal or super flat tube), controlled through I C Vertical C-Correction, controlled through I2C Control of Vertical Amplitude through I C Control of Vertical Position through I2C Input for Vertical Amplitude compensation versus EHV E/W Correction Output (also known as Pin Cushion Output) Horizontal Size Adjustment through I C control of E/W Output DC level Control of E/W (Pincushion) Adjustment through I2C Control of Keystone (Trapezoid) Adjustment through I2C Control of Corner Adjustment through I C Fully integrated Dynamic Horizontal Phase Control Control of Side Pin Balance through Control of Parallelogram through I2C H/V composite Dynamic Focus Output Control of Horizontal Dynamic Focus Amplitude through I2C Control of Horizontal Dynamic Focus Symmetry through I2C Control of Vertical Dynamic Focus Amplitude through I2C Tracking of Geometric Corrections and of Vertical focus with Vertical Amplitude and Position Control of Horizontal and Vertical Moire cancellations through I C Optimisation of HMoire frequency through I2C B+ Regulation, adjustable through I C Stand-by function, disabling H and V scanning and B+ X-Ray protection, disabling H scanning and B+ Blanking Outputs Fast I2C Read/Write I 2C indication of the presence of Syncs (biased from 5V alone) I2C indication of the polarity and Type of Syncs I2C indication of Lock/Unlock, for both Horizontal and Vertical sections
2 2 2 2 2 2 2
Value YES YES NO 15 to 80 1 to 3.5 f0 NO NO YES 30 to 65 NO YES NO 35 to 150 50 to 120 YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES NO 400 YES YES YES
Unit
kHz
%
Hz Hz
I2C
kHz
4/43
BLOCK DIAGRAM
PLL1F 7
POSITION 8
R0 C0 6 5
HFLY 12
PLL2C 4 Phase Shifter H-Duty (7bits)
HOUT 26 Hout Buffer Safety Processor 11 19 17 29 25 HGND VGND GND VCC XRAY
Phase/Frequency Comparator H-Phase(7bits) H/HVIN 1 VSYNCIN 2 Sync Input Select (1bit) VSYNC Sync Processor
VCO
Phase Comparator
Lock/Unlock Identification
SPin bal 7bits x2 B+ Controller x
HFLY
28 +OUT 16 ISENSE 14 COMP 15 REGIN
+
HMOIRE 3 /HLOCK
HorizontalMoire Generator 7 bits+ON/OFF +Frequency
Key bal 7bits VDFAMP 7bits x2
5V Internal reference (7bits) 10 FOCUS
Geometry Tracking SDA 31 SCL 30 GND 27 5V 32 E/Wpcc 7bits Keyst. 7 bits
Corner 7bits x4 x2
Amp Symmetryx2 2x7bits
7 bits I2C Interface
7 bits Vertical Oscillator Ramp Generator VPOS 7bits
VAMP 7bits
9 HFOCUSCAP
S and C Correction Href Vref
x
24 EWOUT HSize DC 7 bits
HREF 13 VREF 21
VerticalMoire Cancel 7bits+ON/OFF VSYNC
22
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20
VCAP VAGCCAP
18 23 VBREATH OUT V
STV6886
STV6886
STV6886
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VDD Supply Voltage (Pin 29) Supply Voltage (Pin 32) Max Voltage on Pin 4 Pin 9 Pin 5 Pins 6, 7, 8, 14, 15, 16, 20, 22 Pins 3, 10, 18, 23, 24, 25, 26, 28 Pins 1, 2 Pins 30, 31 Human Body Model, 100pF Discharge EIAJ Norm, 200pF Discharge through 0 T stg Tj Toper Storage Temperature Junction Temperature Operating Temperature Parameter Value 13.5 5.7 4.0 5.5 6.4 8.0 VCC VDD 5 2 300 -40, +150 +150 0, +70 Unit V V V V V V V V V kV V C C C
VIN
VESD
ESD susceptibility through 1.5k
THERMAL DATA
Symbol R th(j-a) Parameter Max. Junction-Ambient Thermal Resistance Value 65 Unit C/W
SUPPLY AND REFERENCE VOLTAGES
Electrical Characteristics (VCC = 12V, Tamb = 25C unless otherwise indicated)
Symbol VCC VDD ICC IDD VREF-H VREF-V IREF-H I REF-V Parameter Supply Voltage Supply Voltage Supply Current Supply Current Horizontal Reference Voltage Vertical Reference Voltage Max. Sourced Current on VREF-H Max. Sourced Current on VREF-V Test Conditions Pin 29 Pin 32 Pin 29 Pin 32 Pin 13, I = -2mA Pin 21, I = -2mA Pin 13 Pin 21 7.6 7.6 Min. 10.8 4.5 Typ. 12 5 50 5 8.2 8.2 8.8 8.8 5 5 Max. 13.2 5.5 Units V V mA mA V V mA mA
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STV6886
I2C READ/WRITE
Electrical Characteristics (VDD = 5V, Tamb = 25C)
Symbol I2C PROCESSOR (1) Fscl Tlow Thigh Vinth VACK I2C leak Note: 1 Parameter Test Conditions Pin 30 Pin 30 Pin 30 Pins 30, 31 Pin 31 VDD = 0 Pins 30, 31 = 5 V 1.3 0.6 2.2 0.4 20 Min. Typ. Max. 400 Units kHz s s V V A
Maximum Clock Frequency Low period of the SCL Clock High period of the SCL Clock SDA and SCL Input Threshold Acknowledged Output Voltage on SDA input with 3mA Leakage current into SDA and SCL with no logic supply
See also I2 C Bus Address Table.
SYNC PROCESSOR
Operating Conditions (VDD = 5V, VCC = 12V, Tamb = 25C)
Symbol HSVR MinD Mduty VSVR VSW VSmD VextM Parameter Voltage on H/HVIN Input Minimum Horizontal Input Pulses Duration Maximum Horizontal Input Signal Duty Cycle Voltage on VSYNCIN Minimum Vertical Sync Pulse Width Test Conditions Pin 1 Pin 1 Pin 1 Pin 2 Pin 2 0 5 15 750 Min. 0 0.7 25 5 Typ. Max. 5 Units V s % V s % s
Maximum Vertical Sync Input Duty Cycle Pin 2 Maximum Vertical Sync Width on TTL H/ Pin 1 Vcomposite Parameter Test Conditions Min. 2.2 Typ.
Electrical Characteristics (VDD = 5V, VCC = 12V, Tamb = 25C)
Symbol VINTH RIN VoutT Note: 2 Max. 0.8 250 26 35 Units V V k % Horizontal and Vertical Input Logic Level High Level (Pins 1, 2) Low Level Horizontal and Vertical Pull-Up Resistor Extracted Vsync Integration Time (% of TH) on H/VComposite (2) Pins 1, 2 C0 = 820pF
T H is the horizontal period.
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STV6886
HORIZONTAL SECTION
Operating Conditions
Symbol VCO I0max F(max.) I12m HOI Max Current from Pin 6 Maximum Oscillator Frequency Maximum Input Peak Current Horizontal Drive Output Maximum Current Parameter Delay Time for detecting polarity change(3) VCO Control Voltage (Pin 7) Pin 12 Pin 26, Sunk current Pin 6 1.5 80 5 30 mA kHz mA mA Parameter Test Conditions Min. Typ. Max. Units
OUTPUT SECTION
Electrical Characteristics (VCC = 12V, Tamb = 25C)
Symbol 1st PLL SECTION HpoIT Pin 1 VREF-H = 8.2V fH = f0 fH=fH (Max.) R0 = 6.49k, C0 = 820pF % of Horizontal Period Sub-Address 01 Byte x1111111 Byte x1000000 Byte x0000000 PLL1 Unlocked PLL1 Locked R0 = 6.49k, C0 = 820pF Not including external componant drift fH(Min.) fH(Max.) (6) Sub-address 02 1xxx xxxx 0000 0000 0111 1111 6 0.3 2.75 3 Tbd Tbd 0.75 ms Test Conditions Min. Typ. Max. Units
Vvco
1.4 4.9 15.9 10 2.9 3.5 4.2 140 1 22.8 -150 fo+0.5 3.5fo Tbd Tbd
V V kHz/V %
Vcog Hph
VCO Gain (Pin 7) Horizontal Phase Adjustment (4) Horizontal Phase Setting Value (Pin 8)(4) Minimum Value Typical Value Maximum Value PLL1 Filter Charge Current Free Running Frequency Free Running Frequency Thermal Drift (5) PLL1 Capture Range
Vbmi Vbtyp Vbmax IPII1U IPII1L fo dfo/dT CR
V V V A mA kHz ppm/C kHz kHz V V V
HUnlock
DC level pin 3 when PLL1 is unlocked (7)
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STV6886
Symbol FBth Hjit HDmin HDmax
Parameter Flyback Input Threshold Voltage (Pin 12) Horizontal Jitter (8) Horizontal Drive Output Duty-Cycle (Pin 26) (9) X-RAY Protection Input Threshold Voltage, Internal Clamping Levels on 2nd PLL Loop Filter (Pin 4)
Test Conditions
Min. 0.65
Typ. 0.75 70 30 65
Max.
Units V ppm % %
2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION At 31.4kHz Sub-Address 00 Byte x1111111 Byte x0000000 (10) Pin 25, (see fig. 14) Low Level High Level 7.6
XRAYth Vphi2
8.2 1.6 4.2 7.5
8.8
V V V V
VSCinh
Inhibition threshold (The condition VCC < VSCinh will stop H-Out, V-Out, B-Out and Pin 29 reset X-RAY)
0.4 V HDvd Horizontal Drive Output (low level) Pin 26, IOUT = 30mA Note: 3 This delay is necessary to avoid a wrong detection of polarity change in the case of a composite sync. 4 See Figure 10 for explanation of reference phase. 5 These parameters are not tested on each unit. They are measured during our internal qualification. 6 A larger range may be obtained by application. 7 When at 0xxx xxxx, (HMoire/HLock not selected), Pin 3 is a DAC with 0.3...2.75V range. When at 1xxx xxxx (HMoire/HLock selected) and PLL1 is locked, Pin 3 provides the waveform for HMoire. See also Moire section. 8 9 Hjit = 106x(Standard deviation/Horizontal period). Duty Cycle is the ratio between the output transistor OFF time and the period. The scanning transistor is controlled OFF when the output transistor is OFF. 10 Initial Condition for Safe Start Up.
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STV6886
VERTICAL SECTION
Operating Conditions
Symbol R LOAD Parameter Minimum Load for less than 1% Vertical Amplitude Drift Parameter Voltage at Ramp Bottom Point Voltage at Ramp Top Point (with Sync) Voltage at Ramp Top Point (without Sync) Vertical Sawtooth Discharge Time Vertical Free Running Frequency AUTO-SYNC Frequency (13)
(12)
Test Conditions Pin 20
Min. 65
Typ.
Max.
Units M
Electrical Characteristics (VCC = 12V, Tamb = 25C)
Symbol VRB VRT VRTF VSTD VFRF ASFR RAFD Rlin Test Conditions Pin 22 Pin 22 Pin 22 Pin 22, C22 = 150nF Pin 22, C22 = 150nF C22 = 150nF 5% 50 200 0.5 3.2 3.6 4.0 2.15 3.0 3.9 5 Tbd Min. Typ. 2.1 5.1 VRT0.1 70 100 120 Max. Units V V V s Hz Hz ppm/ Hz % V V V V V V mA
Ramp Amplitude Drift Versus Frequency C22 = 150nF 50Hz< f < 120Hz at Maximum Vertical Amplitude (11) Ramp Linearity on Pin 22 (12) 2.5V < V27 < 4.5V Sub Address 06 Vertical Position Adjustment Voltage (Pin Byte 00000000 23 - VOUT mean value) Byte 01000000 Byte 01111111 Vertical Output Voltage (peak-to-peak on Pin 23) Vertical Output Maximum Current (Pin 23) Max Vertical S-Correction Amplitude (TV Sub Address 07 is the vertical period) Byte 11111111 (0xxxxxxx inhibits S-CORR V/VPP at TV/4 V/VPP at 3TV/4 11111111 gives max S-CORR) Vertical C-Corr Amplitude (0xxxxxxx inhibits C-CORR) DC Breathing Control Range (14) Vertical Output Variation versus DC Breathing Control (Pin 23) Sub Address 08 V/VPP at TV/2 Byte 10000000 Byte 11000000 Byte 11111111 V18 V18 > VREF-V 1VVPOS
Tbd
VOR
Tbd
Tbd
VOI
dVS
-3.5 +3.5
% %
Ccorr
-3 0 +3 12 0 -2.5
% % % V %/V %/V
BRRANG BRADj
Note: 11 These parameters are not tested on each unit. They are measured during our internal qualification procedure. Note: 12 Set Register 07 at Byte 0xxxxxxx (S correction inhibited) and Register 08 at Byte 0xxxxxxx (C correction inhibited), to obtain a vertical sawtooth with linear shape. Note: 13 This is the frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on Pin22 and Pin 20, and with a constant ramp amplitude. Note: 14 When not used, the DC breathing control pin must be connected to 12V.
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STV6886
DYNAMIC FOCUS SECTION
Electrical Characteristics (VCC = 12V, Tamb = 25C)
Symbol Parameter Horizontal Dynamic Focus Sawtooth Minimum Level Maximum Level Horizontal Dynamic Focus Sawtooth Discharge Width Internal Phase Advance versus HFLY middle (Independent of frequency) Bottom DC Output Level DC Output Voltage Thermal Drift Horizontal Dynamic Focus Amplitude HDFamp Max Byte Typ Byte Max Byte Horizontal Dynamic FocusSymmetry (For time reference, see Figure 15) Max Phase Advance Max Phase Delay
(11)
Test Conditions Pin 9, capacitor on HFOCUSCAP and C0 = 820pF, TH = 20s Triggered by HDFstart
Min.
Typ.
Max.
Units
HORIZONTAL DYNAMIC FOCUS FUNCTION (seeFigure 15 on page 28) HDFst 2.2 4.9 400 V V ns s V ppm/C
HDFdis
HDFstart HDFDC TDFHD
1 RLOAD = 10k, Pin 10 Sub-Address 03, Pin 10, fH = 50kHz, Symmetric Wave Form x1111111 x1000000 x0000000 Subaddress 04 x1111111 (decimal 127) x0000000 (decimal 0) 16 16 2.1 200
1 1.5 3.5
VPP VPP VPP
HDFKeyst
% %
VERTICAL DYNAMIC FOCUS FUNCTION (see Figu re 1) Sub-Address 0F Vertical Dynamic Focus Parabola (added Min Byte x0000000 to horizontal) Amplitude with VAMP and Typ Byte x1000000 VPOS Typical Max Byte x1111111 Parabola Amplitude Function of VAMP (tracking between VAMP and VDF) with VPOS Typ. (see Figure 1 on page 15, and (15)) Parabola Asymmetry Function of VPOS Control (tracking between VPOS and VDF) with VAMP Max. B/A Ratio A/B Ratio Sub-Address 05 Byte x0000000 Byte x1000000 Byte x1111111 Sub-Address 06 0 0.5 1 0.6 1 1.5 VPP VPP VPP VPP VPP VPP
AMPVDF
VDFAMP
VHDFKeyt
Byte Byte
x0000000 x1111111
0.52 0.52
Note: 15 S and C correction are inhibited to obtain a linear vertical sawtooth.
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STV6886
GEOMETRY CONTROL SECTION
Electrical Characteristics (VCC = 12V, Tamb = 25C)
Symbol VEWM VEWm Parameter Maximum E/W Output Voltage Minimum E/W Output Voltage For control of Horizontal size. DC Output Voltage with: -E/W Corner inhibited -Keystone inhibited DC Output Voltage Thermal Drift Parabola Amplitude with: -VAMP max, -VPOS typ., -Keystone and Corner inhibited Parabola Amplitude Function of VAMP Control (tracking between VAMP & E/W): -VPOS typ. -E/W Amplitude, Corner & Keystone inhibited (17) Keystone Adjustment Capability with: VPOS typ. -E/W inhibited, -Corner inhibited -Vert. Amplitude max (see (17) and Figure 4) Corner Adjustment Capability with: -VPOS typ, -E/W inhibited -Keystone inhibited -Vertical Amplitude max. Test Conditions Pin 24 Pin 24 Pin 24, see Figure 2 Subaddress 11 Byte x0000000 Byte x1000000 Byte x1111111 See (16) Subaddress 0A Byte 11111111 Byte 11000000 Byte 10000000 Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 1.8 Min. Typ. Max. 6.5 Units V V SYMMETRIC CONTROL THROUGH E/W OUTPUT (see Figure 2 on page 15 and Figure 4 on page 15)
EWDC
2 3.25 4.2 100 1.4 0.7 0
V V V ppm/C VPP VPP VPP VPP VPP VPP
TDEWDC EWpara
EWtrack
0.2 0.4 0.7
KeyAdj
Subaddress 09 Byte 10000000 Byte 11111111
0.4 0.4
VPP VPP
EW Corner
Subaddress 10 Byte 11111111 Byte 11000000 Byte 10000000
+1.25 0 -1.25
VPP VPP VPP
KeyTrack
Intrinsic Keystone Function of VPOS Subaddress 06 Control (tracking between VPOS & E/W): - E/W Amplitude -Vertical Amplitude max -Corner inhibited B/A Ratio Byte 00000000 A/B Ratio Byte 01111111
0.52 0.52
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STV6886
Symbol
Parameter Side Pin Balance Parabola Amplitude (Figure 3) with : -VAMP max., -VPOS typ. -Parallelogram inhibited (17 & 18) Side Pin Balance Parabola Amplitude function of VAMP Control (tracking between VAMP and SPB) with: -SPB max., -VPOS typ. -Parallelogram inhibited (17 & 18) Parallelogram Adjustment Capability with: -VAMP max., -VPOS typ. -SPB inhibited (17 & 18)
Test Conditions Subaddress 0D
Min.
Typ.
Max.
Units
ASYMMETRIC CONTROL THROUGH INTERNAL DYNAMIC HORIZONTAL PHASE MODULATION (see Figure 3)
SPBpara
Byte 11111111 Byte 10000000 Subaddress 05
+2.8 -2.8
%T H %T H
SPBtrack
Byte 10000000 Byte 11000000 Byte 11111111 Subaddress 0E
1 1.8 2.8
%T H %T H %T H
ParAdj
Byte 11111111 Byte 11000000
+2.8 -2.8
%T H %T H
Intrinsic Parallelogram Function of VPOS Subaddress 06 Control (tracking between VPOS and DHPC) with : -VAMP max., Partrack -SPB max. -Parallelogram inhibited (17 & 18) B/A Ratio Byte x0000000 0.52 A/B Ratio Byte x1111111 0.52 Note: 16 These parameters are not tested on each unit. They are measured during our internal qualification procedure. Note: 17 With Register 07 at Byte 0xxxxxxx (S correction inhibited) and Register 08 at Byte 0xxxxxxx (C correction inhibited), the sawtooth has a linear shape.
MOIRE CANCELLATION SECTION
Electrical Characteristics (V CC = 12V, Tamb = 25C)
Symbol RMOIRE Parameter Minimum Output Resistor to GND Test Conditions Pin 3 RMOIRE = 4.7k sub-address 02 Byte 00000000 Byte 01000000 Byte 01111111 RMOIRE = 4.7k Sub-address 02 Byte 10000000 Byte 11000000 Byte 11111111 Sub-address II: 0xxx xxxx 1xxx xxxx Sub-address 0C Byte 11111111 Min. 4.7 Typ. Max. Units k HORIZONTAL AND VERTICAL MOIRE
DacOut
DC Voltage pin 3 DAC configuration
0.3 1.1 2.75
3
V V V
HMOIRE
Moire pulse (See also Hunlock in 1st PLL section) H Frequency: Locked
0 0.8 2.2 Separate Combined 3
VPP VPP VPP
THMOIRE VMOIRE
Preferred Scanning/EHT structure Vertical Moire (measured on VOUT: Pin 23)
mV
Note: 18 TH is the horizontal period.
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STV6886
B+ SECTION
Operating Conditions
Symbol FeedRes Parameter Minimum Feedback Resistor Test Conditions Resistor between Pins 15 and 14 Test Conditions At low frequency (19) See
(19)
Min. 5
Typ.
Max.
Units k
Electrical Characteristics (VCC = 12V, Tamb = 25C)
Symbol OLG UGBW IRI Parameter Error Amplifier Open Loop Gain Unity Gain Bandwidth Feedback Input Bias Current Min. Typ. 85 6 0.2 1.4 2 3 1.3 1 100 0.25 5 +20 -20 6 100 V A % V V % % V ns Max. Units dB MHz A mA mA
Current sourced by Pin 15 (PNP base) Current sourced by Pin 14 Current sunk by Pin 14 (20) Pin 16
EAOI CSG MCEth ISI Tonmax B+OSV IVREF V REFADJ PWMSEL tFB+
Error Amplifier Output Current Current Sense Input Voltage Gain
Max Current Sense Input Threshold VoltPin 16 age Current Sense Input Bias Current Current sunk by Pin 16 (PNP base)
Maximum ON Time of the external power % of horizontal period, transistor fo = 27kHz) (21) B+Output Saturation Voltage Internal Reference Voltage Internal Reference Voltage Adjustment Range V28 with I28 = 10mA On error amp (+) input Subaddress OB: Byte 1000000 Byte 01111111 Byte 00000000
Threshold for step-up/step-down selection (step-up configuration if V16 < PWM- Pin 16 SEL) Fall Time Pin 28
Note: 19 These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches coming from corners of our process and also temperature characterization. Note: 20 To make soft start possible, 0.5mA are sunk when B+ is disabled. Note: 21 The external power transistor is OFF during 400ns of the HFOCUSCAP discharge
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STV6886
Figure 1. Vertical Dynamic Focus Function
Figure 2. E/W Output
Figure 3. Dynamic Horizontal Phase Control
Figure 4. Keystone Effect on E/W Output (PCC Inhibited)
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STV6886
TYPICAL OUTPUT WAVEFORMS
Function Sub Address Pin Byte Specification V OUTDC 10000000 2.15V Effect on Screen
Vertical Size
05
23 11111111
V OUTDC 3.9V
00000000 Vertical Position DC Control
VOUTDC = 3.2V
06
23
01000000
VOUTDC = 3.6V
01111111
V OUTDC = 4.0V
0xxxxxxx: Inhibited Vertical S Linearity 07 23 V 11111111 VPP
V = 3.5% VPP
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STV6886
Function
Sub Address
Pin
Byte
Specification
Effect on Screen
0xxxxxxx : Inhibited
Vertical C Linearity
08
23
V 10000000 VPP DV =-3% VPP
11111111
V PP DV =+3% VPP
x1111111 4.2V Horizontal Size 11 24 x0000000 2V
Horizontal Dynamic Focus with: Amplitude
03
10 X000 0000 -- X111 1111 ---
Horizontal Dynamic Focus with: Symmetry
04
10
X000 0000 -- X111 1111 ---
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STV6886
Function
Sub Address
Pin
Byte
Specification (E/W + Corner Inhibited)
Effect on Screen
10000000 Keystone (Trapezoid) Control 09 24
0.4V
EW DC
11111111
0.4V
EWDC
(Keystone + Corner Inhibited) 10000000 0A 24 11111111
EWDC EWDC 0V
E/W (Pin Cushion) Control
1.4V
(Keystone+ E/W Inhibited)
11111111 Corner Control
1.25V EW DC
10
24
EW DC
10000000
1.25V
Parallelogram Control
Internal
(SPB Inhibited) 10000000
2.8% T H
0E
11111111
2.8% T H
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STV6886
Function
Sub Address
Pin
Byte (Parallelogram Inhibited)
Specification
Effect on Screen
Side Pin Balance Control
0D
10000000
2.8% TH
11111111
2.8% TH
X111 1111 Vertical Dynamic Focus with Horizontal
2.1V TV
0F
10
X000 0000 2.1V TV 0V
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STV6886
I2C BUS ADDRESS TABLE Slave Address (8C): Write Mode Sub Address Definition
D8 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 D3 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 D2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Horizontal Drive Selection/Horizontal Duty Cycle X-ray Reset/Horizontal Position Horizontal Moire/H Lock Sync. Priority/Horizontal Focus Amplitude Refresh/Horizontal Focus Symmetry Vertical Ramp Amplitude Vertical Position Adjustment S Correction C Correction E/W Keystone E/W Amplitude B+ Reference Adjustment Vertical Moire Side Pin Balance Parallelogram Vertical Dynamic Focus Amplitude E/W Corner H. Moire Frequency/Horizontal Size Amplitude
Slave Address (8D): Read Mode: No sub address needed.
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STV6886
I2C BUS ADDRESS TABLE (continued)
D8 WRITE MODE 00 HDrive 0, off [1], on Xray 1, reset [0] HMoire/HLock 1, on [0], off Sync 0, Comp [1], Sep Detect Refresh [0], off Vramp 0, off [1], on Test V 1, on [0], off S Select 1, on [0] C Select 1, on [0] E/W Key 0, off [1] E/W Sel 0, off [1] Test H 1, on [0], off V. Moire 1, on [0] SPB Sel 0, off [1] Parallelo 0, off [1] Horizontal Duty Cycle [0] [0] [0] [0] [0] [0] [0] D7 D6 D5 D4 D3 D2 D1
Horizontal Phase Adjustment [1] [0] [0] [0] [0] [0] [0]
01
Horizontal Moire Amplitude [0] [0] [0] [0] [0] [0] [0]
02
Horizontal Focus Amplitude [1] [0] [0] [0] [0] [0] [0]
03
Horizontal Focus Symmetry [1] [0] [0] [0] [0] [0] [0]
04
Vertical Ramp Amplitu de Adjustment [1] [0] [0] [0] [0] [0] [0]
05
Vertical Position Adjustment [1] [0] [0] [0] S Correction [1] [0] [0] [0] C Correction [1] [0] [0] [0] E/W Keystone [1] [0] [0] [0] E/W Amplitude [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]
06
07
08
09
0A
B + Reference Adjustment [1] [0] [0] [0] [0] [0] [0]
0B
Vertical Moire Amplitude [0] [0] [0] [0] Side Pin Balance [1] [0] [0] [0] Parallelogram [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]
0C
0D
0E
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STV6886
D8 0F Eq. Pulse 1, ignore TH/2 [0], accept all Corner Sel 1, on [0], off H. Moire suited to 1 Combined [0] Separate scanning/EHT Hlock 0, on [1], no
D7 [1]
D6 [0]
D5 [0]
D4 [0] E/W Corner
D3 [0]
D2 [0]
D1 [0]
Vertical Dynamic Focus Amplitude
10
[1]
[0]
[0]
[0]
[0]
[0]
[0]
Horizontal Size Amplitude [1] [0] [0] [0] [0] [0] [0]
11
READ MODE Vlock 0, on [1], no Xray 1, on [0], off Polarity Detection Sync Detection H/V det [0], no det V det [0], no det H/V pol V pol Vext det [1], negative [1], negative [0], no det
[x] at Power-on Reset value Data is transferred with vertical sawtooth retrace. We recommend setting the unspecified bits to [0] in order to ensure compatibility with future devices.
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STV6886
OPERATING DESCRIPTION 1 GENERAL CONSIDERATIONS
1.1 Power Supply The typical values of the power supply voltages VCC and VDD are 12 V and 5 V respectively. Optimum operation is obtained for VCC between 10.8 and 13.2 V and VDD between 4.5 and 5.5 V. In order to avoid erratic operation of the circuit during the transient phase of VCC switching on, or off, the value of V CC is monitored: if VCC is less than 7.5 V typ., the outputs of the circuit are inhibited. Similarly, before VDD reaches 4 V, all the I2 C register are reset to their default value (see I2C Bus Address Table). In order to have very good power supply rejection, the circuit is internally supplied by several voltage references (typ. value: 8.2 V). Two of these voltage references are externally accessible, one for the vertical and one for the horizontal part. They can be used to bias external circuitry (if ILOAD is less than 5 mA). It is necessary to filter the voltage references by external capacitors connected to the respective grounds, in order to minimize the noise and consequently the "jitter" on vertical and horizontal output signals. 1.2 I2C Control STV6886 belongs to the I2C-controlled device family. Instead of being controlled by DC voltages on dedicated control pins, each adjustment can be done via the I2C Interface. The I2C bus is a serial bus with a clock and a data input. The general function and the bus protocol are specified in the Philips-bus data sheets. The inputs (Data and Clock) are comparators with a 2.2 V threshold at 5 V supply. Spikes of up to 50 ns are filtered by an integrator and the maximum clock speed is limited to 400 kHz. The data line (SDA) can receive or transmit data. In read-mode the IC sends reply information (1 byte) to the micro-processor. The bus protocol prescribes a full-byte transmission in all cases. The first byte after the start condition is used to transmit the IC-address (hexa 8C for write, 8D for read). 1.3 Write Mode In write mode the second byte is the subaddress of the selected function to adjust (or controls to affect) and the third byte the corresponding data byte. It is possible to send more than one data byte to the IC. If after the third byte no stop or start condition is detected, the circuit increments automatically by one the momentary subaddress in the subaddress counter (auto-increment mode). So it is possible to transmit immediately the following data bytes without sending the IC address or subaddress. This can be useful to reinitialize all the controls very quickly (flash manner). This procedure can be finished by a stop condition. The circuit has 18 adjustment capabilities: 3 for the horizontal part, 4 for the vertical, 3 for the E/W correction, 2 for the dynamic horizontal phase control, 2 for the vertical and horizontal Moire options, 3 for the horizontal and the vertical dynamic focus and 1 for the B+ reference adjustment. 18 bits are also dedicated to several controls (ON/ OFF, Horizontal Forced Frequency, Sync Priority, Detection Refresh and XRAY reset). 1.4 Read Mode During the read mode the second byte transmits the reply information. The reply byte contains the horizontal and vertical lock/unlock status, the XRAY activation status, and the horizontal and vertical polarity detection. It also contains the sync detection status which is used by the MCU to assign the sync priority. A stop condition always stops all the activities of the bus decoder and switches to high impedance both the data and clock line (SDA and SCL). See I2C Bus Address Table. 1.5 Sync Processor The internal sync processor allows the STV6886 to accept: - separated horizontal & vertical TTL-compatible sync signal - composite horizontal & vertical TTL-compatible sync signal 1.6 Sync Identification Status The MCU can read (address read mode: 8D) the status register via the I2C bus, and then select the sync priority depending on this status. Among other data this register indicates the presence of sync pulses on H/HVIN, VSYNCIN and (when 12 V is supplied) whether a Vext has been extracted from H/HVIN. Both horizontal and vertical sync are detected even if only 5 V is supplied.
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STV6886
In order to choose the right sync priority the MCU may proceed as follows (see I2C Bus Address Table): - refresh the status register, - wait at least for 20ms (Max. vertical period), - read the status register. Sync priority choice should be :
Vextd et No Yes H/V det Yes Yes V det Yes No Sync priority Subaddress 03 (D8) 1 0 Comment Sync type Separated H&V Composite TTL H&V
ing horizontal sync. Its level goes to low when locked. This information is also available on pin 3 if sub-address 02 D8 is equal to 1. When PLL1 is unlocked, pin 3 output voltage becomes higher than 6V. When it is locked, the HMoire waveform is available on pin 3 (max voltage: 3V).
2 HORIZONTAL PART
2.1 Internal Input Conditions A digital signal (horizontal sync pulse or TTL composite) is sent by the sync processor to the horizontal input. It may be positive or negative (see Figure 5). Using internal integration, both signals are recognized if Z/T < 25%. Synchronization takes place on the leading edge of the internal sync signal. The minimum value of Z is 0.7 s. Another integration is able to extract the vertical pulse from composite sync if the duty cycle is higher than 25% (typically d = 35%), (see Figure 6). Figure 5.
Of course, when the choice is made, we can refresh the sync detections and verify that the extracted Vsync is present and that no sync type change has occurred. The sync processor also gives sync polarity information. 1.7 IC status The IC can inform the MCU about the 1st horizontal PLL and vertical section status (locked or not) and about the XRAY protection (activated or not).Resetting the XRAY internal latch can be done either by decreasing the VCC supply or directly resetting it via the I 2C interface. 1.8 Sync Inputs Both H/HVIN and VSYNCIN inputs are TTL compatible triggers with hysteresis to avoid erratic detection. Both inputs include a pull up resistor connected to VDD. 1.9 Sync Processor Output The sync processor indicates on bit D8 of the status register whether 1st PLL is locked to an incomFigure 6.
CSync
Integ. d VSyn
The last feature performed is the removal of these equalization pulses which fall in the middle of a line, to avoid parasitic pulses on the phase comparator (which would be disturbed by missing or ex-
traneous pulses). This last feature is switched on/ off by sub-address 0F D8. By default [0], equalization pulses will not be removed.
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STV6886
2.2 PLL1 The PLL1 consists of a phase comparator, an external filter and a voltage-controlled oscillator (VCO).The phase comparator is a "phase/frequency" type designed in CMOS technology. This kind of phase detector avoids locking on wrong frequencies. It is followed by a "charge pump", composed of two current sources : sunk and sourced (typically I =1 mA when locked and I = 140 A when unlocked). This difference between lock/unlock allows smooth catching of the horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system when PLL1 is locked, avoiding the horizontal frequency changing too quickly. The dynamic behavior of PLL1 is fixed by an external filter which integrates the current of the charge pump. A "CRC" filter is generally used (see Figure 7 on page 25).
Figure 7. PLL1F 7
1.8k
10nF
The PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong pulses on phase comparator. Inhibition is obtained by stopping high and low signals at the input of the charge pump block (see Figure 8 on page 25).
Figure 8.
Lock/Unlock Status Extracted VSync PLL1F 7 LOCKDET High PLL INHIBITION CHARGE PUMP Low Extracted VSync PHASE ADJUST HPOSITION OSC IC HPOS Adj.
2
R0 6
C0 5
H/HVIN 1
INPUT INTERFACE
COMP1
VCO
Figure 9.
I0 I0 PLL1F 7 (Loop Filter) 6 (1.4V1.6V 0 0.875 TH 6.4V
2
6.4V
RS FLIP FLOP
1.6V
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STV6886
The VCO uses an external RC network. It delivers a linear sawtooth obtained by the charge and the discharge of the capacitor, with a current proportional to the current in the resistor. The typical thresholds of the sawtooth are 1.6 V and 6.4 V. The control voltage of the VCO is between 1.4 V and 4.9 V (see Figure 9). The theoretical frequency range of this VCO is in the ratio of 1 to 3.5. The effective frequency range has to be smaller due to clamp intervention on the filter lowest value. The sync frequency must always be higher than the free running frequency. For example, when using a sync range between 25 kHz and 80 kHz, the suggested free running frequency is 22 kHz. PLL1 ensures the coincidence between the leading edge of the sync signal and a phase reference REF1 obtained by comparison between the sawtooth of the VCO and an internal DC voltage Vb. Vb is I2C adjustable between 2.9 V and 4.2 V (corresponding to 10 %) (see Figure 10). The STV6886 also includes a Lock/Unlock identification block which senses in real time whether PLL1 is locked or not on the incoming horizontal sync signal. This information is available through I2C, and also on pin 3 if HLock/Unlock option has been set through Subaddress 02,D8. Figure 10. PLL1 Timing Diagram
H O SC Sawtooth
Figure 11. PLL2 Timing Diagram
HOsc Sawtooth
7/8TH
1/8 TH
6.4V 4.0V
1.6V
Flyback Internally shaped Flyback HDrive Ts Duty Cycle
7/8 TH
The phase comparator of PLL2 is followed by a charge pump (typical output current: 0.5 mA). The flyback input consists of an NPN transistor. The input current must be limited to less than 5 mA (see Figure 12). Figure 12. Flyback Input Electrical Diagram
1/8 TH
6.4V Ref. for H Position Vb (2.9V500
HFLY 12 20k Q1
Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.9 V and 4.2 V. The PLL1 ensures the exact coincidence between the signal phase REF and HSYNC. A 10% TH phase adjustment is possible around the 3.5V point.
GND 0V
2.3 PLL2 PLL2 ensures a constant position of the shaped flyback signal in comparison with the sawtooth of the VCO, taking into account the saturation time Ts (see Figure 11 on page 26)
The duty cycle is adjustable through I2C from 30 % to 65 %. For a safe start-up operation, the initial duty cycle (after power-on reset) is 65% in order to avoid having too long a conduction period of the horizontal scanning transistor. The maximum storage time (Ts Max.) is (0.44THTFLY/2). Typically, TFLY/TH is around 20 %, at maximum frequency, which means that Ts max is around 34 % of TH.
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STV6886
2.4 Output Section The H-drive signal is sent to the output through a shaping stage which also controls the H-drive duty cycle (I2C adjustable) (see Figure 11). In order to secure the scanning power part operation, the output is inhibited in the following cases: - when VCC or VDD are too low - when the XRAY protection is activated - during the Horizontal flyback - when the HDrive I2C bit control is off. The output stage consists of a NPN bipolar transistor. Only the collector is accessible (see Figure 13). Figure 13.
This output stage is intended for "reverse" base control, where setting the output NPN in off-state will control the power scanning transistor in offstate. The maximum output current is 30mA, and the corresponding voltage drop of the output VCEsat is 0.4V Max.
Obviously the power scanning transistor cannot be directly driven by the integrated circuit. An interface has to be added between the circuit and the power transistor either of bipolar or MOS type. 2.5 X-RAY Protection The X-Ray protection is activated by application of a high level on the X-Ray input (more than 8.2V on Pin 25). It inhibits the H-Drive and B+ outputs. This activation is internally delayed by 2 lines to avoid erratic detection when short parasitics are present . This protection is latched; it may be reset either by VCC switch-off or by I2C (see Figure 14 on page 28). 2.6 Horizontal and Vertical Dynamic Focus For dynamic focus adjustment, the STV6886 delivers the sum of two signals on pin 10: - a parabolic waveform at horizontal frequency, - a parabolic waveform at vertical frequency. The horizontal parabola comes from a sawtooth in phase advance with flyback pulse middle. The phase advance versus horizontal flyback middle is kept constant versus frequency (about 1s). Symmetry and amplitude are I2C adjustable (see Figure 15 on page 28). The vertical parabola is tracked with VPOS and VAMP. Its amplitude can be adjusted. It is also affected by S and C corrections. This positive signal once amplified is to be sent to the CRT focusing grids. Because the DC/DC converter is triggered by the HFocus sawtooth, it is recommended to connect a capacitor to pin 9, even if HFocus is not needed. The capacitor value is critical only if Focus is used.
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STV6886
Figure 14. Safety Functions Block Diagram
Figure 15. Phase of HFocus Parabola
Flyback pulse
1 s 0.4 s
H Focus sawtooth
0.6 s 0.6 s 127
64 H Focus parabola 45 0
I2C Code (decimal)
0.475TH 0.16TH 0.16TH 127 28/43 64 45 0
STV6886
2.7 Horizontal Moire Output The Horizontal Moire output is intended to correct a beat between the horizontal video pixel period and the CRT pixel width. The Moire signal is a combination of the horizontal and vertical frequency signals. To achieve a Moire cancellation, the Moire output has to be connected so as to modulate the horizontal position. We recommend introducing this "Horizontal Controlled Jitter" on the ground side of PLL2 capacitor where this "controlled jitter" will directly affect the horizontal position. The amplitude of the signal is I2C adjustable. The H-Moire frequency can be chosen via the I2C. If H Scanning and EHT are separated, bit D8 in subaddress 11 should be set to 0. If H Scanning and EHT are combined, setting this bit to 1 will provide a better screen aspect. The H-Moire output is combined with the PLL1 horizontal unlock output. If HMoire/HLock is selected (bit 02D8 to 1): - when PLL1 is unlocked, pin 3 output voltage goes above 6V. - when PLL1 is locked, the HMoire signal (up to 2.2V peak) is present on pin 3. If HMoire/HLock is not selected, pin 3 can be used as a 0....2.5V DAC.
3 VERTICAL PART
3.1 Function When the synchronization pulse is not present, an internal current source sets the free-running frequency. For an external capacitor C OSC = 150nF, the typical free running frequency is 100Hz. The typical free running frequency can be calculated by: 1 fo(Hz) = 1.5 . 10-5 . C
OSC
A negative or positive TTL level pulse applied on Pin 2 (VSYNC) as well as a TTL composite sync on Pin 1 can synchronize the ramp in the range [fmin, fmax] (See Figure 16 on page 30). This frequency range depends on the external capacitor connected on Pin 22. A 150nF ( 5%) capacitor is recommended for 50Hz to 120Hz applications.
If a synchronization pulse is applied, the internal oscillator is synchronized immediately but with wrong amplitude. An internal correction then adjusts it in less than half a second. The top value of the ramp (Pin 22) is sampled on the AGC capacitor (Pin 20) at each clock pulse and a transconductance amplifier modifies the charge current of the capacitor so as to adjust the amplitude to the right value. The Read Status register provides the vertical Lock-Unlock and the vertical sync polarity information. We recommend to use an AGC capacitor with low leakage current. A value lower than 100nA is mandatory. A good stability of the internal closed loop is reached with a 470nF 5% capacitor value on Pin 20 (VAGC). 3.2 I2C Control Adjustments S and C correction shapes can then be added to this ramp. These frequency-independent S and C corrections are generated internally. Their amplitudes are adjustable by their respective I2C registers. They can also be inhibited by their select bits. Finally, the amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude control register. The adjusted ramp is available on Pin 23 (VOUT) to drive an external power stage. The gain of this stage can be adjusted ( 25%) depending on its register value. The mean value of this ramp is driven by its own I2C register (vertical position). Its value is VPOS = 7/16 . VREF-V 400mV. Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from VREF-V, the bias voltage sent to the noninverting input of the booster should also derive from VREF-V to optimize the accuracy (see Application Diagram). 3.3 Vertical Moire By using the vertical Moire, VPOS can be modulated from frame to frame. This function is intended to cancel the fringes which appear when the line to line interval is very close to the CRT vertical pitch. The amplitude of the modulation is controlled by register VMOIRE on sub-address 0C and can be switched-off via the control bit D8.
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STV6886
Figure 16. AGC Loop Block Diagram
3.4 Basic Equations In first approximation, the amplitude of the ramp on Pin 23 (VOUT) is: VOUT - VPOS = (VOSC - VDCMID) . (1 + 0.3 (VAMP )) where: VDCMID = 7/16 VREF (middle value of the ramp on Pin 22, typically 3.6V) VOSC = V22 (ramp with fixed amplitude) VAMP = -1 for minimum vertical amplitude register value and +1 for maximum VPOS is calculated by: VPOS = VDCMID + 0.4 VP where VP = -1 for minimum vertical position register value and +1 for maximum. The current available on Pin 22 is: IOSC = 3. VREF x COSC x f 8
where COSC = capacitor connected on Pin 22 and f = synchronization frequency.
3.5 Geometric Corrections The principle is represented in Figure 17 on page 31. Starting from the vertical ramp, a parabola-shaped current is generated for E/W correction (also known as Pin Cushion correction), dynamic horizontal phase control correction, and vertical dynamic focus correction. The parabola generator is made by an analog multiplier, the output current of which is equal to: DI = k .(VOUT - VDCMID)2 where VOUT is the vertical output ramp (typically between 2 and 5V) and VDCMID is 3.6V (for VREF-V = 8.2V). The VOUT sawtooth is typically centered on 3.6V. By changing the vertical position, the sawtooth shifts by 0.4V. To provide good screen geometry for any enduser adjustment, the STV6886 has the "geometry tracking" feature which automatically adapts the parabola shape, depending on the vertical position and size.
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STV6886
Due to the large output stage voltage range (E/W Pin Cushion, Keystone, E/W Corner), the combination of the tracking function, maximum vertical amplitude, maximum or minimum vertical position and maximum gain on the DAC control may lead to output stage saturation. This must be avoided by limiting the output voltage with appropriate I2C register values. For the E/W part and the dynamic horizontal phase control part, a sawtooth-shaped differential current in the following form is generated: I' = k' . (VOUT - VDCMID) Then I and I' are added and converted into voltage for the E/W part. Figure 17. Geometric Corrections Principle
Each of the three E/W components or the two dynamic horizontal phase control components may be inhibited by their own I2C select bit. The E/W parabola is available on Pin 24 via an emitter follower output stage which has to be biased by an external resistor (10k to ground). Being stable in temperature, the device can be DC coupled with external circuitry (mandatory to obtain H Size control). The vertical dynamic focus is combined with the horizontal focus on Pin 10. The dynamic horizontal phase control drives internally the H-position, moving the HFLY position on the horizontal sawtooth in the range of 2.8 %TH both for side pin balance and parallelogram.
3.6 E/W EWOUT = EWDC + K1 (VOUT - VDCMID) + K2 (VOUT - VDCMID)2+ K3 (VOUT - VDCMID)4
K1 is adjustable by the keystone I2C register. K2 is adjustable by the E/W amplitude I2C register. K3 is adjustable by the E/W corner I2C register.
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3.7 Dynamic Horizontal Phase Control IOUT= K4 (VOUT - VDCMID) + K5 (VOUT - VDCMID)2 K4 is adjustable by the parallelogram I2C register. K5 is adjustable by the side pin balance I2C register.
4 DC/DC CONVERTER PART
This unit controls the switch-mode DC/DC converter. It converts a DC constant voltage into the B+ voltage (roughly proportional to the horizontal frequency) necessary for the horizontal scanning. This DC/DC converter can be configured either in step-up or step-down mode. In both cases it operates very similarly to the well known UC3842. 4.1 Step-up Configuration Operating Description - The power MOS is switched ON during the flyback (at the beginning of the positive slope of the horizontal focus sawtooth). - The power MOS is switched OFF when its current reaches a predetermined value. For this purpose, a sense resistor is inserted in its source. The voltage on this resistor is sent to Pin16 (ISENSE). - The feedback (coming either from the EHV or from the flyback) is divided to a voltage close to 5.0V and compared to the internal 5.0V reference (IVREF). The difference is amplified by an error amplifier, the output of which controls the power MOS switch-off current. Main Features - Switching synchronized on the horizontal frequency, - B+ voltage always higher than the DC source, - Current limited on a pulse-by-pulse basis. The DC/DC converter is disabled: - when VCC or VDD are too low, - when X-Ray protection is latched, - directly through I2C bus. When disabled, BOUT is driven to GND by a 0.5mA current source. This feature allows to implement externally a soft start circuit.
4.2 Step-down Configuration In step-down configuration, the ISENSE information is not used any more and therefore not sent to the Pin16. This configuration is selected by connecting this Pin16 to a DC voltage higher than 6V (for example VREF-V). Instead of ISENSE waveform the H-Focus Sawtooth is used for comparison with the amplified error voltage. For that reason, the Step-down configuration can operate only if the H-Focus capacitor is connected. Operating Description - The power MOS is switched ON as for the stepup configuration. - The feedback to the error amplifier is done as for the step-up configuration. - The power MOS is switched OFF when the HFOCUSCAP voltage gets higher than the error amplifier output voltage. Main Features - Switching synchronized on the horizontal frequency, - B+ voltage always lower than the DC source, - No current limitation. 4.3 Step-up and Step-down Configuration Comparison In step-down configuration the control signal is inverted compared with the step-up mode.This, for the following reason: - In step-up mode, the switch is a N-channel MOS referenced to ground and made conductive by a high level on its gate. - In step-down, a high-side switch is necessary. It can be either a P- or a N-channel MOS. * For a P-channel MOS, the gate is controlled directly from Pin 28 through a capacitor (this allows to spare a Transformer). In this case, a negative-going pulse is needed to make the MOS conductive. Therefore it is necessary to invert the control signal. * For a N-channel MOS, a transformer is needed to control the gate. The polarity of the transformer can be easily adapted to the negative-going control pulse.
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Figure 18. DC/DC Converter (represented: Step-Up configuration)
DAC 7bits Horizontal Dynamic Focus Sawtooth
+ 1/3 1.3V 1.3V + C1 down down C2 up B+ Inhibit. 6V + C4 S R Q up
I adjust 8.2V 5V 20%
+
85 dB -A
HDF Discharge 400ns
BOUT
12V
28
-
+ C3 -
Command step-up/down
-
REGIN
15
COMP
14
ISENSE
16
STV6886
22k EHV Feedback
1M
10nF
L
VB+
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INTERNAL SCHEMATICS
Figure 19. Figure 22.
12V
5V 20 k
HREF 13
Pins 1-2 H/HVIN VSYNCIN
200
CO 5
Figure 20.
Figure 23.
HREF 13 12V HREF 13
12V
R0 6 HMOIRE/HLOCK 3
Figure 21.
12V HREF 13
Figure 24.
PLL1F 7 PLL2 4
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STV6886
Figure 25.
HREF 12V
Figure 28.
HREF 13 12V
HPOSITION
8 HFLY 12
Figure 26.
Figure 29.
12V HFOCUS 9 CAP
HREF 13
COMP 14
Figure 27.
12V
Figure 30.
12V 12V
REGIN 15 HFOCUS 10
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STV6886
Figure 31.
Figure 34.
12V
12V VCAP 22
ISENSE 16
Figure 32.
12V
Figure 35.
12V BREATH
18
VOUT 23
Figure 33.
Figure 36.
12V
12V EWOUT VAGCCAP 20
24
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STV6886
Figure 37.
12V
XRAY
25
Figure 38.
V12
HOUT-BOUT Pins 26-28
Figure 39.
Pins 30-31 SDA-SCL
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STV6886
Figure 40. Demonstration Board
J16 J15 1 J14 2 34 C39 22pF R29 4.7k R42 100 R 41 1 00
+12V CC 2 10F CC3 47pF CC1 100nF TP13 PC1 47k TP17 J1 2 -12V 9 J11
TP1
IC4 STV6886
1 H/HV IN
+5V +5V L1 22H R39 4.7k C32 100nF
TP16 2 VSYN CIN TP10 3 HMOIRE/ HLOCK C7 22nF 4 PLL2C C 28 820pF 5% 5 C0
+5V 32 C 30 1 00F SDA 31
C40 22pF SCL SDA 1 3 14 15 16 17 18 19 20 21 22 23 24 PWM4 PWM5 SCL SDA XTALOUT RST GND R G B TEST PWM6 PWM7 C45 10F IC3-STV9422 R49 22k +5V
16 1 5 14 13 12 11 10 VCC 1 TA1 TB1 TA2 2 IA CDB TB2 CDA 3 4 IB IA 5 IB QA 6 QB QA 7
SCL 30
ICC1 MC1 4528
8
QB GND
HSYNC V DD
XTALIN
CKOUT
VSYNC
PWM3
PWM2
PWM1
PWM0
PXCK
FBLK
VCC 29 C6 100nF B+OUT 28
C5 100F
+12V
12 1 1 10 9 X1
8
7
6
5
4
3
2
1 R43 10k
CC4 47pF +12V PC2 47k R35 +12V 10k HOU T J8 C22 33pF R8 10k R1 0 10k C25 33pF
TILT J13
R23 6.49k 1% 6 R0 C1 3 10nF 7 PLL1F C31 4.7F R36 1 .8k 8H XRAY25 POSITION 9 HFOCUS- EWOUT 24 CAP VOUT 23 HOUT 26 GND 27
+12 V R53 1k HOUT C49 100nF
R56 560k C48 10F D2 1N4148
8MHz C38 33pF
C37 33pF
C4 3 +5V 47F
C 42 1F R30 10k E/W POWER STAGE
R7 10k R45 33k
C36 1F
+12V R37 27k R3 4 1k R15 1k R17 43k
C1 7 1F
HFLY J9 DYN FOCUS
R25 1k R24 10k L 47H
C34 820pF 5%
Q1 Q2 BC557 BC557
R19 270k C11 220pF R18 10k
R38 2.2 3W
J1 E/W
10 FOCUS OUT 11 HGND
+12V C12 VC AP 22 150nF R52 3 .9k
R9 47 0
R 33 4 .7k
Q3 TIP122
J19 1 2 3 4 C ON4
C 16 (*) C27 47F C3 3 HR EF 10 0nF
12 HFLY
VREF 21 C15
C3 47F R2 5.6 R40 36k
13 HR EF VAGCCAP 20 JP1 C51 100nF R57 82 k C 47 1 00pF 16 ISENSE B+GND 17 R50 1M C46 1nF
C2 470nF 10 0nF
C4 100nF
C14 470F D1 1n400 1 C10 1 00F 3 5V
C9 100nF TP6
+12V -12 V TP4 TP3
J2 J3
TP7 C1 R3 2 20nF 1.5
14 COMP
VGND 19 IC1 TDA817 2 C10 -12V 470F
J6 1 R11 VYOKE 2 220 0.5W 3 J18 R4 1 0.5W
REGIN R51 1k
15 REGIN
BRE ATH18
R1 12k
I SENSE GND
C41 470pF
C8 100nF R 5 5 .6
R 58 10 B+OUT R73 R75 1M 10k R76 47k P1 10k +12V R74 10k R77 15k C6 0 10 0nF
Q4 BC557
VERTIC AL DEFLEC TION STAGE
J17 HOU T L3 22H
Q5 BC547 C50 10F
TP8 EHT COMP
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STV6886
Figure 41.
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STV6886
Figure 42.
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STV6886
PACKAGE MECHANICAL DATA
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STV6886
PACKAGE MECHANICAL DATA 32 PINS - PLASTIC SHRINK
E E1
A2
A1
A
C L B B1 e Stand-off eA eB D 32 17 1 16 Millimeters Min. 3.556 0.508 3.048 0.356 0.762 .203 27.43 9.906 7.620 3.556 0.457 1.016 0.254 27.94 10.41 8.890 1.778 10.16 12.70 2.540 3.048 3.810 0.100 0.120 4.572 0.584 1.397 0.356 28.45 11.05 9.398 Typ. 3.759 Max. 5.080 Min. 0.140 0.020 0.120 0.014 0.030 0.008 1.080 0.390 0.300 0.140 0.018 0.040 0.010 1.100 0.410 0.350 0.070 0.400 0.500 0.150 0.180 0.023 0.055 0.014 1.120 0.435 0.370
Dimensions A A1 A2 B B1 C D E E1 e eA eB L
Inches Typ. 0.148 Max. 0.200
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change witho ut notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. (c) 2000 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philip s I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philip s. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - FInland - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www .st.com
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